The present invention relates to a semiconductor IC device and in particular, to a technique which is useful when it is applied to a semiconductor IC device using ferroelectric material.
DRAMs (Dynamic Random Access Memories) are widely used as semiconductor memory devices, which can be integrated in a high degree. A DRAM includes an array of memory cells, each of which comprises a series circuit consisting of an MISFET for memory cell selection and a capacitor element for information storage. One (1) bit of information is stored in each of these memory cells.
Recently, as the degree of integration has increased, research and development have been carried out, using a ferroelectric material layer for the dielectric layer in the capacitor element for information storage of the memory cell in the DRAM. The ferroelectric material layer is made of, e.g., lead zirconate titanate, by means of which an amount of stored charge about ten times as great as that obtained by means of a conventional dielectric layer made of silicon oxide can be obtained. That is, by using a ferroelectric material layer, since the amount of charge stored by the capacitor element for information storage in the memory cell can be increased, it is possible to reduce the area occupied by a memory cell and thus to increase the degree of integration of the DRAM. Further the .alpha.-ray soft error withstand voltage of the DRAM can be improved by using the ferroelectric material layer. Still further, by using the ferroelectric material layer, since it is possible to omit the refresh operation (rewriting operation), it is possible to increase operation speed of the storage device.
In the ferroelectric material layer described above, when a voltage is applied between two electrodes of the capacitor element for information storage, the polarization direction thereof varies, tracing a hysteresis loop. The information writing operation is executed by applying a writing voltage, which is higher than the polarization reversal voltage, between the two electrodes of the capacitor element for information storage in the memory cell in the selected state. The polarization reversal voltage is a voltage at which the polarization direction of the ferroelectric material layer begins to be reversed.
For example, in a DRAM, for which the planar structure is adopted, one of the electrodes of the capacitor element for information storage in the memory cell is composed of a semiconductor region. This semiconductor region is formed in one body with one of the semiconductor regions of the MISFET for the memory cell selection, electrically connected therewith. The other electrode of the capacitor element for information storage is composed of a plate electrode disposed on the semiconductor region described above, opposite thereto. This plate electrode is formed in one body with the plate electrodes of the capacitor elements for information storage in the other memory cells, electrically connected therewith. That is, they are constructed in the form of a common plate over the whole region of the memory cell array.
In this DRAM, for which the planar structure is adopted, in the information writing operation described above, a writing voltage, which is higher than the polarization reversal voltage, e.g., of about 5 V is applied to the common plate electrode. For the memory cell in the selected state, a writing voltage, e.g. of 0 V is applied to the data line and a selecting voltage e.g., of 5 V is applied to the word line. On the other hand, for the memory cell in the unselected state a non-writing voltage of about 5 V or the writing voltage of 0 V is applied to the data line and the unselecting voltage of 5 V or a unselecting voltage of 0 V is applied to the word line.
However, in the DRAM having the common plate electrode as described above, when the voltage on a data line in an unselected memory cell is raised from 0 V to 5 V for a reading operation, with the data line and a word line in the unselected memory cell being supplied with 5 V and the common plate electrode being supplied with 0 V in a previous writing operation, a voltage higher than the polarization several voltage is applied between the electrodes of the information storage capacitor element in the course of a rise of the voltage on the data line from 0 V to 5 V. For this reason, since the information written previously in the memory cell by the information writing operation is reversed in the unselected state (the polarization direction is reversed), the information stored in the memory cell is destroyed.
As a technique for solving such technical problems, a technique is proposed, by which the common plate described above is divided into a plurality of lines, each of which corresponds to one data line (complementary data line), and drive lines are constructed so as to be able to supply the writing voltage and the non-writing voltage independently to the divided lines. These drive lines extend in the direction parallel to the direction in which the data lines extend. Further, each of the drive lines is constructed as a drive line common to the other electrodes of all the capacitor elements for information storage in a plurality of memory cells connected with one data line.
In the DRAM to which this technique is applied, in the information writing operation, the writing voltage (e.g., 0 V) is applied to the data line and the writing voltage (e.g., 5 V) is applied to the other electrode of the capacitor element for information storage through the drive line for the memory cell in the selected state. On the other hand, for the memory cell in the unselected state, the non-writing voltage (e.g., 0 V) is applied to the data line and the non-writing voltage (e.g., 0 V) is applied to the other electrode of the capacitor element for information storage through the drive line. That is, since no voltage higher than the polarization reversal voltage is applied between the two electrodes of the capacitor element for information storage in the memory cell in the unselected state, no destruction of information described above takes place.
The technique described above, by which the drive lines are disposed, is reported e.g. in 1989 IEEE ISSCC, Feb. 17, 1989, pp. 242-243. Further a non-volatile memory, in which a ferroelectric material layer is used in each memory cell, is disclosed in JP-A-62-185376 (published Aug. 13, 1987).